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S3C9228/P9228 A/D CONVERTER
14-3
Conversion Data Register ADDATAH/ADDATAL
D1H/D2H, Page 0, Read Only
.9 .8 .7 .6 .5 .4 .3 .2MSB LSB (ADDATAH)
- - - - - - .1 .0MSB LSB (ADDATAL)
Figure 14-2. A/D Converter Data Register (ADDATAH/ADDATAL)
INTERNAL REFERENCE VOLTAGE LEVELS
In the ADC function block, the analog input voltage level is compared to the reference voltage. The analog input
level must remain within the range V
SS
to V
DD
.
Different reference voltage levels are generated internally along the resistor tree during the analog conversion
process for each conversion step. The reference voltage level for the first conversion bit is always 1/2 V
DD
.
BLOCK DIAGRAM
Input Pins
AD0-AD3
(P1.0-P1.3)
Clock
Selector
Conversion Result
(ADDATAH/ADDATAL,
D1H/D2H, Page 0)
-
+
To ADCON.3
(EOC Flag)
Successive
Approximation
Logic & Register
VDD
VSS
Analog
Comparator
10-bit D/A
Converter
M
U
X
ADCON.4-5
(Select one input pin of the assigned pins)
P1CON
(Assign Pins to ADC Input)
ADCON.0
(AD/C Enable)
ADCON.0
(AD/C Enable)
.
.
.
ADCON.2-.1
Figure 14-3. A/D Converter Functional Block Diagram
- USER'S MANUAL 1
- S3C9228/P9228 2
- Important Notice 3
- Table of Contents 6
- Table of Contents (Continued) 7
- Table of Contents (Concluded) 10
- List of Figures 12
- List of Figures (Continued) 13
- List of Figures (Concluded) 15
- List of Tables 16
- List of Programming Tips 18
- List of Register Descriptions 20
- 1 PRODUCT OVERVIEW 23
- FEATURES 24
- ADC — Add With Carry 107
- ADD — Add 108
- AND — Logical AND 109
- CALL — Call Procedure 110
- CCF — Complement Carry Flag 111
- CLR — Clear 112
- COM — Complement 113
- CP — Compare 114
- DEC — Decrement 115
- DI — Disable Interrupts 116
- EI — Enable Interrupts 117
- IDLE — Idle Operation 118
- INC — Increment 119
- IRET — Interrupt Return 120
- JP — Jump 121
- JR — Jump Relative 122
- LD — Load 123
- LDC/LDE — Load Memory 125
- — Load Memory and Decrement 127
- — Load Memory and Increment 128
- NOP — No Operation 129
- OR — Logical OR 130
- POP — Pop From Stack 131
- PUSH — Push To Stack 132
- RCF — Reset Carry Flag 133
- RET — Return 134
- RL — Rotate Left 135
- — Rotate Left Through Carry 136
- RR — Rotate Right 137
- Rotate Right Through Carry 138
- SBC — Subtract With Carry 139
- SCF — Set Carry Flag 140
- SRA — Shift Right Arithmetic 141
- STOP — Stop Operation 142
- SUB — Subtract 143
- Test Complement Under Mask 144
- TM — Test Under Mask 145
- XOR — Logical Exclusive OR 146
- 7 CLOCK CIRCUITS 147
- S3C9228/P9228 CLOCK CIRCUITS 149
- CLOCK CIRCUITS S3C9228/P9228 152
- 8 RESETRESET and POWER-DOWN 155
- POWER-DOWN MODES 156
- 9 I/O PORTS 161
- S3C9228/P9228 I/O PORTS 163
- 10 BASIC TIMER 177
- 11 TIMER 1 181
- S3C9228/P9228 TIMER 1 183
- TIMER 1 S3C9228/P9228 184
- 12 WATCH TIMER 191
- WATCH TIMER CIRCUIT DIAGRAM 193
- WATCH TIMER S3C9228/P9228 194
- 13 LCD CONTROLLER/DRIVER 195
- LCD CIRCUIT DIAGRAM 196
- LCD PORT CONTROL REGISTER 199
- 0 1 2 3 74 65 0 1 2 3 74 65 201
- OVERVIEW 205
- FUNCTION DESCRIPTION 205
- BLOCK DIAGRAM 207
- SS ≤ ADC input ≤ VDD) 208
- 15 SERIAL I/O INTERFACE 209
- SIO BLOCK DIAGRAM 211
- 16 ELECTRICAL DATA 213
- INTHtINTL 220
- DD-0.1 V 223
- ELECTRICAL DATA S3C9228/P9228 226
- 17 MECHANICAL DATA 227
- 44-QFP-1010B 228
- 18 S3P9228 OTP 229
- (42-SDIP) 230
- S3C9228/P9228 S3P9228 OTP 231
- S3P9228 OTP S3C9228/P9228 234
- 19 DEVELOPMENT TOOLS 235
- TB9228 TARGET BOARD 237
- PIN ASSIGNMENTS 246
- PIN DESCRIPTIONS 248
- PIN CIRCUIT DIAGRAMS 250
- 2 ADDRESS SPACES 255
- PROGRAM MEMORY (ROM) 256
- REGISTER ARCHITECTURE 257
- ADDRESS SPACES S3C9228/P9228 258
- SYSTEM STACK 259
- 3 ADDRESSING MODES 261
- (see Figure 3-9) 267
- Program Memory 269
- 4 CONTROL REGISTERS 273
- FLAGS - System Flags Register 276
- — System Flags Register D5H 280
- — SIO Control Register E1H 305
- – Stop Control Register E0H 306
- — System Mode Register DFH 307
- 5 INTERRUPT STRUCTURE 311
- 6 SAM88RCRI INSTRUCTION SET 317
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