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Ref# 420826 Intel
®
Atom™ processor CE4100 5
Platform Design Guide
Intel Confidential
9 High Definition Video Capture (HDVCAP) ................................126
9.1 HDVCAP Signals Interface ...................................................................... 126
9.2 HDVCAP Routing Topology......................................................................128
9.2.1 HDVCAP Design Topology 1........................................................ 128
9.2.2 HDVCAP Design Topology 2........................................................ 129
10 Platform Clock D
esign Guidelines............................................130
10.1 Reference Clock Routing Guidelines ......................................................... 132
10.1.1 CK505 Clock Topology...............................................................132
10.1.2 1IDT6V49061 Clock Topology..................................................... 133
10.2 Audio Reference Clock Output Routing Recommendation ............................136
10.3 VCXO Mode Design Guidelines ................................................................137
- Platform Design Guide 1
- May 2010 1
- Intel Confidential 1
- Legal Statements 2
- Contents 3
- Atom™ processor CE4100 5 5
- List of Tables 6
- Atom™ processor CE4100 7 7
- List of Figures 8
- Atom™ processor CE4100 9 9
- Revision History 10
- Ref# 420826 Intel 11
- Platform Design Guide 11
- Intel Confidential 11
- 1.1 Related Documents 12
- 14 Intel 14
- Acronym Definition 15
- 16 Intel 16
- 18 Intel 18
- 20 Intel 20
- 22 Intel 22
- 24 Intel 24
- 3.1.1 1080 Prepreg 25
- 3.1.4 Break Out Traces 26
- 4.1 Platform Power Rails 27
- 28 Intel 28
- 4.3 Power Decoupling 29
- 4.4 Power Sequence 31
- 32 Intel 32
- 4.5 Reset Sequence 33
- 4.5.1.1 Warm Reset Sequence 34
- 36 Intel 36
- 4.6 Straps 37
- 38 Intel 38
- Topology 39
- 4.7.2 Design Example Two 40
- 4.8 Debug Port Guidelines 41
- Table 5 44
- Routing Guidelines 46
- 52 Intel 52
- 58 Intel 58
- 60 Intel 60
- 62 Intel 62
- 5.7 VREF Circuit 65
- 6.1 Video DAC Interface 67
- 68 Intel 68
- VDACDOUT_P/M 70
- 1.1k1.1k 70
- Caution! 71
- 72 Intel 72
- 74 Intel 74
- Sodaville Package 75
- 76 Intel 76
- 78 Intel 78
- 80 Intel 80
- 82 Intel 82
- 7.1 Overview 85
- S Audio Input Interface 85
- S Audio Output Interface 86
- 7.4 S/PDIF Audio Interface 87
- 88 Intel 88
- TL=TL1+TL2+TL3 89
- 90 Intel 90
- 8.1.3 SATA Test Note 93
- 8.2 USB 2.0 94
- 96 Intel 96
- USBRBIASP 97
- USBRBIASN 97
- Notes: 97
- 8.2.1.3 USB Power Sequence 98
- 8.3 Gigabit Ethernet 99
- 8.4 Expansion Bus Interface 103
- Guidelines 103
- EXP_IO_WRB 105
- 8.4.3 Data Bus A 106
- 8.5 NAND Flash 108
- 8.5.3 NAND_IO Topology 109
- NAND_ALE Topology 110
- 8.5.5 NAND_CE_N Topology 111
- Sodaville 112
- C* Interface 114
- 8.7 UART Interface 115
- 8.8 GPIO Interface 118
- 8.9 SPI Serial Interface 120
- SodavilleSodaville 121
- Recommendation 122
- 8.10 Smart Card Interface 124
- 126 Intel 126
- 9.2 HDVCAP Routing Topology 128
- 130 Intel 130
- 10.1.1 CK505 Clock Topology 132
- RS=33+/-5% 134
- RT=55+/-5% 134
- IDT6V49601 135
- Routing Recommendation 136
- 138 Intel 138
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